As the geometries of VLSI circuits continue to decrease, the corresponding delays of the CMOS gates in these devices also decrease. The resistance of a routing wire increases as the width of the wire decreases, thus the routing delays decrease at a slower rate than logic delays as geometries shrink, which causes the ratio of routing delay to logic delay to increase with each device generation. Therefore, there is a need for a more accurate clock skew analysis methodology to ensure maximum frequency operation of an electronic circuit design. While designers attempt to make the delays uniform across clock network resources, static and dynamic component delay variations can occur due to process, voltage and temperature differences across the integrated circuit (IC). In order to provide for more accurate clock skew analysis in view of these variations, clock skew analysis often uses both the maximum and minimum delay values. While methods have been explored to increase the accuracy of clock skew calculations, these methods may be time and resource intensive or produce results that are biased toward worst-case clock skews.
The present invention may address one or more of the above issues.